Review of the week: conception, low consumption

Cadence unveiled Cerebrus Intelligent Chip Explorer, a new machine learning-based tool to drive the Cadence RTL implementation flow through to approval. The tool aims to use reinforcement learning to find flow solutions that otherwise could not be explored and apply models to future designs. The company claims it can improve productivity by up to 10X and PPA by up to 20% with stream optimization for many blocks simultaneously. Renesas and Samsung Foundry noted the use of Cerebrus.

Ansys announced improvements in the latest version of its tool suite, Ansys 2021 R2. In semiconductors, 2021 R2 provides advanced power analysis (APA) ready at 3nm and improves the efficiency of voltage drop correction by 3, using the identification of the aggressor, the analysis of simulation and links to Engineering Change Order (ECO) tools. Ansys said that 2021 R2 improves base time and cost efficiency by 4X when using the cloud for semiconductor simulation. In addition, the new Phi Plus mesh generator speeds up initial meshing for lead wire box electromagnetism and signal integrity analysis by 6-10 times on average. New and improved Chip-Package-System and PCB workflows are also available with automation for IC-on-Package and multi-zone PCBs with rigid flexible cables.

Aldec launched an ASIC / SoC physical prototyping and hardware emulation board that can accommodate designs up to approximately 83 million ASIC gates. HES-VU19PD-ZU7EV only uses two FPGAs to provide logic to simplify partitioning. For larger designs, four boards can be connected. The logic module FPGAs are both Virtex UltraScale + VU19P devices and also include a Zynq UltraScale + ZU7EV MPSoC as a host module. It also includes a PCIe switch device that provides PCIe x16 Gen 3 connections with the logical devices and PCIe x8 Gen 3 connections with the FPGA controller.

Imperas software updated its free riscvOVPsimPlus reference model with support for the nearly ratified RISC-V P extension and architectural validation test suites. The P (or Packed SIMD / DSP) extension supports real-time data processing applications as part of the main processor pipeline without the need for a coprocessor. riscvOVPsimPlus is an envelope model that can be configured to cover all ratified RISC-V specifications and standard extensions and includes several architectural validation test suites, which form a basic test plan for software tier compatibility in specification definitions.

Synopsis’ VC Functional Safety Manager, which provides automation for Functional Safety Failure Mode Effects Analysis (FMEA) and Failure Mode Effects Diagnostic Analysis (FMEDA) for automotive SoCs, has received new functionalities within the framework of a collaboration with Samsung Foundry. It now supports top-down flow and what-if analysis for early exploration of security architecture, rapid synthesis for RTL design data extraction, support for lifecycle management tools application life and management of failure modes and fault injection in the analog parts of the SoC.

Ansys Power Library (APL), a tool for characterizing design libraries and calculating chip power and reliability, is now available for the Arm Neoverse architecture to support development on AWS Graviton2 processors.

Gowin Semiconductor has released an Image Signal Processor (ISP) IP portfolio and benchmark design for its FPGAs. Targeting affordable camera products, the ISP IP takes pixel data from an image sensor and adjusts it via CFA (Color Filter Array / Debayer), CCM (Color Correction Array), Gamma Correction and AE (Auto Exposure) ) and AWB (Auto White Balance)) to provide a balanced image. It provides 8-bit / 10-bit image data and provides an adjustable register map for different image sensors and resolutions.

THIS WILL RivieraWaves Bluetooth 5.3 IP is now available as a complete hardware / software solution for new designs and as a software upgrade only for existing compatible designs. Improvements to Bluetooth 5.3 include increased protocol efficiency, link strength, and wireless security.

Infineon has launched high-density radiation tolerant NOR Flash (RadTol) products for space-class FPGAs. 256MB and 512MB NOR Flash conforms to MIL-PRF-38535 QML-V stream, the highest quality and reliability standard certification for aerospace-grade integrated circuits and target applications such as FPGA configuration , image storage, microcontroller data, and boot code storage. The devices are tolerant to radiation up to 30 krad (Si) polarized and 125 krad (Si) unpolarized. At 125 ° C, the devices support 1,000 program / erase cycles and 30 years of data retention and at 85 ° C 10,000 program / erase cycles with 250 years of data retention.

Cross bars Resistive RAM (ReRAM) technology can be used as a non-clonable physical function (PUF) to generate cryptographic keys. The company said using ReRAM instead of SRAM for PUFs provides a higher level of randomness, low bit error rate, resistance to invasive attacks, and the ability to handle a range of variations. environmental.

by Winbond OctalNAND Flash memory is now interoperable with Synopsis’ DesignWare Synchronous Serial Interface (SSI) IP for a complete NAND flash solution with high-speed read bandwidth in densities up to 4 Gbit targeted for automotive, mobile and IoT SoCs.

Embedded, peripheral and IoT
Dolphin design and CEA List formed a joint R&D lab for embedded systems with the aim of identifying ideal tradeoffs in advanced AI devices. CEA-List’s PNeuro hardware accelerator integrates AI into the computing platform developed in the joint laboratory and is associated with the processing platform developed by Dolphin Design. Dolphin Design has also integrated several hardware IPs developed by CEA-List into its Chameleon and Raptor product portfolio.

Infineon launched a family of single-stage flyback controllers with constant voltage output optimized for economical smart LED drivers. The ICL88xx family targets LED lighting applications, such as LED drivers and luminaires up to 125W, smart lighting and emergency luminaires, as well as adapters and chargers, flat TVs, all-in-one PCs. -one and monitors up to 125 W.

HPC and quantum computing
the US Department of Energy is investing $ 28 million in funding for five research projects aimed at making the most of high-performance computing resources. Projects will focus on computational methods, algorithms and software to advance chemical and materials research, in particular to simulate quantum phenomena and chemical reactions. “The DOE National Laboratories are home to some of the fastest supercomputers in the world, and with more advanced software, we can fully harness the power of these supercomputers to make groundbreaking discoveries and solve the world’s most difficult problems,” said US Secretary of Energy Jennifer M. Granholm.

One of the projects, led by University of California Riverside and Lawrence Berkeley National Laboratory, aims to use high performance exascale computing to control hardware systems with light. “Almost all chemical, material and biological processes occur out of equilibrium, and understanding how these systems can be controlled with light can enable many technologies such as solar materials, sensors and light harvesting nanomaterials.” said Bryan Wong, professor of materials science and engineering at UC Riverside.

As part of separate funding, the DOE will spend $ 13 million on five projects to adapt scientific software to run on the next generation of supercomputers.

The EU is also working to improve the way software works on supercomputers. The ADMIRE project, coordinated by the Carlos III University of Madrid (UC3M) and funded by the European Joint Undertaking for High Performance Computing (EuroHPC JU) and the Participating States, is developing a new adaptive storage system for high performance computing. Part of the effort includes creating ad hoc storage systems, tools to adjust the resources used by a program, optimization of process pipelines, and the ability to process, compress, and analyze data during running simulations. . The project hopes to improve the runtime of data-intensive applications in areas such as weather forecasting, molecular dynamics, turbulence modeling, mapping, brain research, and software cataloging.

Quantum Computing Startup Xanadu received a DARPA grant to develop a unique general purpose “circuit breaker” compiler that can automatically decompose a circuit into a hybrid multicircuit model to take advantage of both classical and quantum computing. This would allow for larger scale calculations without requiring more powerful quantum processors. “Using these tools, we plan to run quantum algorithms that would natively require over 100 qubits using quantum hardware and simulators containing only 10 to 30 qubits,” said Nathan Killoran, who leads the team. Quantum Software & Algorithms from Xanadu.

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